View ISL6363IRTZ_8392911.PDF datasheet online --- IC-ON-LINE

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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011, 2013. all rights reserved intersil (and design) and r3 technology are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. multiphase pwm regulator for vr12? desktop cpus isl6363 fully compliant with vr12? specifications, the isl6363 provides a complete solution for microprocessor core and graphics power supplies. it provides two voltage regulators (vrs) with three integrated gate drivers. the first output (vr1) can be configured as a 4, 3, 2 or 1-phase vr while the second output (vr2) is a 1-phase vr. the two vrs share a serial control bus to communicate with the cpu and achieve lower cost and smaller board area compared with a two-chip approach. based on intersil?s robust ripple regulator r3 technology?, the pwm modulator, compared to traditional modulators, has faster transient settling time, variable switching frequency during load transients and has improved light load efficiency with its ability to automatically change switching frequency. the isl6363 has several other key features. both outputs support dcr current sensing with a single ntc thermistor for dcr temperature compensation or accurate resistor current sensing. both outputs come with remote voltage sensing, programmable v boot voltage, serial bus address, imax, tmax, adjustable switching frequency, oc protection and separate power-good indicators. to reduce output capacitors, the isl6363 also has an additional compensation function for ps1/2 mode and high frequency load transient compensation. features ? serial data bus (svid) ?dual outputs: - configurable 4, 3, 2 or 1-phase for the 1st output with 2 integrated gate drivers - 1-phase for the 2nd output with integrated gate driver ? precision core voltage regulation - 0.5% system accuracy over-temperature - enhanced load line accuracy ? ps2 compensation and high frequency load transient compensation ? differential remote voltage sensing ? lossless inductor dcr current sensing ?programmable v boot voltage at start-up ? resistor programmable address, imax, tmax for both outputs ? adaptive body diode conduction time reduction applications ?vr12 desktop computers related literature ? isl6363eval1z user guide figure 1. fast transient response figure 2. accurate loadline, v core vs i out v core 50mv/div comp 1v/div 1v/div 65a step load 2s/div 0.90 0.95 1.00 1.05 1.10 1.15 0 5 10152025303540455055606570758085 i out (a) v core (v) 1.1v - ps1 1.1v - ps0 1.7m ? loadline september 5, 2013 fn6898.1 n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
isl6363 2 fn6898.1 september 5, 2013 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6363crtz isl6363 crtz 0 to +70 48 ld 6x6 tqfn l48.6x6 ISL6363IRTZ isl6363 irtz -40 to +85 48 ld 6x6 tqfn l48.6x6 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6363 . for more information on msl please see techbrief tb363 . pin configuration isl6363 (48 ld tqfn) top view pin descriptions isl6363 symbol description bottom pad gnd common ground signal of the ic. unless otherwise stated, si gnals are referenced to the gnd pin. the pad should also be used as the thermal pad for heat dissipation. 1 scomp this pin is a placeholder for potential future functionality. this pin can be left floating. 2 pgood power-good open-drain output indicating when vr1 is ab le to supply a regulated voltage. pull-up externally with a 680 ? resistor to +5v or 1k ? to +3.3v. 3 vcc +5v bias supply pin. connect a high quality 0.1f capacitor fr om this pin to gnd and place it as close to the pin as possib le. a small resistor (2.2 ? for example) between the +5v supply and the decoupling capacitor is recommended. 4, 5 isump, isumn vr1 current sense input pins for current monito ring, droop current and overcurrent detection. 6 isen1 vr1 phase 1 current sense input pin for phase current balancing. 7 isen2 vr1 phase 2 current sense input pin for phase current balancing. 8 isen3 vr1 phase 3 current sense input pin for phase current balancing. temporary pinout subject to change 25 26 27 28 29 30 31 32 33 34 38 37 40 39 42 41 44 43 46 45 12 11 10 9 8 7 6 5 4 3 23 24 21 22 19 20 17 18 15 16 sclk alert# sda vr_on imon vw comp psicomp vsen isen4 isen3 isen1 isumn isump pwm3 boot2 pvcc lgate1 isumpg isumng ntcg pvccg lgateg bootg vcc vr_hot# phase2 pgood lgate2 pwm4 13 14 2 1 48 47 35 36 fbg compg rtng vwg imong pgoodg rtn isen2 ugate1 phase1 addr ugateg phaseg fb ntc ugate2 boot1 scomp gnd pad (bottom)
isl6363 3 fn6898.1 september 5, 2013 9 isen4 vr1 phase 4 current sense input pin for phase current balancing. 10 vsen vr1 remote core voltage sense input. 11 psicomp this pin is used for improving transient response in ps2/3 mode of vr1 by switching in an additional type 3 compensati on network to improve system gain and phase margin. connect a resi stor and capacitor from this pi n to the output of vr1 near the feedback compensation network. 12 rtn vr1 remote voltage sensing return input. connec t this pin to the remote ground sensing location. 13 fb inverting input of the error amplifier for vr1. 14 comp this is a dual function pin. this pin is the output of the error amplifier for vr1. a resistor connected from this pin to gnd programs imax for vr1 and v boot for both vr1 and vr2. refer to table 7 on page 28. 15 vw a resistor from this pin to comp programs the pwm switching frequency for vr1. 16 ntc one of the thermistor network inputs to the thermal monito ring circuit used to control th e vr_hot# signal. use this pin to monitor the temperature of vr1. place the ntc close to the desired thermal detection point on the pcb. 17 imon current monitoring output pin for vr1. the current sense sign al from isumn and isump is output on this pin to generate a voltage proportional to the output current of vr1. 18 vr_on enable input signal for the controller. a high level logic signal on this pin enables the controller and initiates soft- start for vr1 and vr2. 19, 20, 21 sda, alert#, sclk data, alert and clock signal for the svid commu nication bus between the cpu and vr1 and vr2. 22 pgoodg power-good open-drain output indicating when vr2 is ab le to supply a regulated voltage. pull-up externally with a 680 ? resistor to +5v or 1.0k ? to 3.3v. 23 imong current monitoring output pin for vr2. the current sense si gnal from isumng and isumpg is output on this pin to generate a voltage proportional to the output current of vr2. 24 vwg a resistor from this pin to compg programs the pwm switching frequency for vr1. 25 compg this is a dual function pin. this pin is the output of the error amplifier for vr2. a resistor connected from this pin t o gnd programs imax for vr2 and tmax for both vr1 and vr2. refer to table 8 on page 28. 26 fbg inverting input of the error amplifier for vr2. 27 rtng vr2 remote voltage sensing return input. connec t this pin to the remote ground sensing location. 28, 29 isumpg, isumng vr2 current sense input pin for current monito ring, droop current and overcurrent detection. 30 ntcg one of the thermistor network inputs to the thermal monito ring circuit used to control th e vr_hot# signal. use this pin t o monitor the temperature of vr2. place the ntc close to the desired thermal detection point on the pcb. 31 vr_hot# open drain thermal overload output indicator. 32 pvccg input voltage bias for the internal gate driver for vr2. connect +12v to this pin. decouple with at least a 1f mlcc cap acitor and place it as close to the pin as possible. 33 lgateg output of the vr2 low-side mosfet gate driver. co nnect this pin to the gate of the vr2 low-side mosfet. 34 bootg connect a mlcc capacitor from this pi n to the phaseg pin. the boot capacitor is charged through an internal boot diode connected from the pvccg pin to the bootg pin. 35 ugateg output of the vr2 high-side mosf et gate drive. connect this pin to the gate of the vr2 high-side mosfet. 36 phaseg current return path for the vr2 high -side mosfet gate driver. connect this pin to the node connecting the source of the high-side mosfet, the drain of the low-side mosfet and the output inductor of vr2. 37 pwm4 pwm output for phase 4 of vr1. when pwm4 is pulled to +5v vcc, the controller will disable phase 4 of vr1. 38 pwm3 pwm output for phase 3 of vr1. when pwm3 is pulled to +5v vcc, the controller will disable phase 3 of vr1. 39 phase2 current return path for the vr1 phase 2 high-side mosfet gate driver. connect this pin to the node connecting the sourc e of the high-side mosfet, the drain of the low-side mosfet and the output inductor of phase 2. 40 ugate2 output of the vr1 phase 2 high-side mosfet gate drive. co nnect this pin to the gate of the high-side mosfet of phase 2. pin descriptions (continued) isl6363 symbol description
isl6363 4 fn6898.1 september 5, 2013 41 boot2 connect an mlcc capacitor from this pin to the phase2 pin. the boot capacitor is charged through an internal boot diode connected from the pvccg pin to the bootg pin. 42 lgate2 output of the vr1 phase 2 low-side mosfet gate driver. co nnect this pin to the gate of the low-side mosfet of phase 2. 43 pvcc input voltage bias for the internal gate drivers for vr1. connect +12v to this pin. decouple with at least a 1f mlcc cap acitor and place it as close to the pin as possible. 44 lgate1 output of the vr1 phase 1 low-side mosfet gate driver. co nnect this pin to the gate of the low-side mosfet of phase 1. 45 boot1 connect an mlcc capacitor from this pin to the phase1 pin. the boot capacitor is charged through an internal boot diode connected from the pvcc pin to the boot1 pin. 46 ugate1 output of the vr1 phase 1 high-side mosfet gate drive. co nnect this pin to the gate of the high-side mosfet of phase 1. 47 phase1 current return path for the vr1 phase 1 high-side mosfet gate driver. connect this pin to the node connecting the sourc e of the high-side mosfet, the drain of the low-side mosfet and the output inductor of phase 1. 48 addr a resistor from this pin to gnd programs the sv id address for vr1 and vr2. refer to table 9 on page 28. pin descriptions (continued) isl6363 symbol description
isl6363 5 fn6898.1 september 5, 2013 block diagram rtn e/a fb idroop current sense isump isumn comp driver driver lgate1 phase1 ugate1 boot1 vw pvccg ov fault pgood _ + _ + + + driver driver lgate2 phase2 ugate2 boot2 ibal fault oc fault pwm3 isen3 isen2 isen1 current balancing digital interface sda alert# sclk driver driver lgateg phaseg ugateg bootg ov fault pgoodg oc fault mode1 dac1 mode2 dac2 temp monitor ntcg ntc vr_hot# t_monitor imax vboot tmax set (a/d) addr addr comp vr_on mode d/a a/d imon imong vready rtng 6 e/a fbg idroopg current sense isumpg isumng compg vr2 modulator vwg _ + _ + + + vr1 modulator psicomp circuit vcc gnd imon imong pwm4 isen4 psicomp comp compg compg pvcc vsen scomp
isl6363 6 fn6898.1 september 5, 2013 simplified application circuit rdroop vr_on pgood vsssense vccsense rntc o c vw fb vr_on comp rtn pgood ntc rntcg o c ntcg sda sda alert# alert# sclk sclk gnd pvcc rprog1 pgoodg pgoodg vr_hot# vr_hot# isl6363 l2 l1 isen4 phase2 ugate2 rsum3 rsum2 rn cn ri l3 rsum4 boot2 +12v vcc ugate lgate phase boot pwm pvcc gnd isl6622 lgate2 isen2 phase1 ugate1 boot1 lgate1 pwm3 isump isumn o c risen3 risen2 risen4 isen1 vsumn cisen4 cisen3 cisen2 cvsumv lg gx vcore ugateg rng cng rig rsumg bootg vin lgateg isumpg isumng o c vsumng cvsumng cpu vcore phaseg vcc imong imong imon imon +5v +12v pvccg l4 +12v vcc ugate lgate phase boot pwm pvcc gnd isl6622 vin +12v pwm4 rsum1 risen1 isen3 cisen1 psicomp vsen raddr addr rfset rdroopg vsssenseg vccsenseg vwg fbg compg rtng rprog2 rfsetg rscomp scomp
isl6363 7 fn6898.1 september 5, 2013 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 gate driver timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 multiphase r3 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 start-up timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 voltage regulation and load line implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 differential voltage sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 phase current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 dynamic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vr_hot#/alert# behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 psicomp function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 adaptive body diode conduction time reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 supported data and configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 key component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 inductor dcr current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 resistor current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 programming resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ntc network on the ntc and the ntcg pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 optional slew rate compensation circuit for 1-tick vid transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
isl6363 8 fn6898.1 september 5, 2013 absolute maximum rating s thermal information supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v supply voltage, pvcc, pvccg . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v absolute boot voltage (boot). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +36v phase voltage (phase) . . . . . . . . . . . . . . . . . . -8v (<400ns, 20j) to +30v, (<200ns, v boot - vgnd < +36v) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . phase-0.3v to boot + 0.3v phase-3.5v (<100ns pulse width, 2j) to boot + 0.3v lgate voltage . . . . . . . . . . . . -3v (<20ns pulse width, 5j) to pvcc + 0.3v -5v (<100ns pulse width, 2j) to pvcc + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to (vcc + 0.3v) open drain outputs, pgood, vr_hot#, alert#. . . . . . . . . . -0.3v to +7v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . 2500v machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 250v charged device model (tested per jesd22-c101a) . . . . . . . . . . 1000v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 48 ld tqfn package (notes 4, 5) . . . . . . . 27 1 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% pvcc, pvccg voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v ambient temperature crtz (commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c irtz (industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vcc = 5v, pvcc = 12v, pvccg = 12v, t a = 0c to +70c, (commercial) or -40c to +85c (industrial), f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, 0c to +70c (commercial) or -40c to +85c (industrial). parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vcc vr_on = 1v 18 20 ma vr_on = 0v 4.1 5.5 ma pvcc supply current i pvcc vr_on = 1v 1 2 ma vr_on = 0v 1 ma pvccg supply current i pvccg vr_on = 1v 1 2 ma vr_on = 0v 1 ma vcc power-on-reset threshold por r v cc rising 4.35 4.5 v por f v cc falling 4 4.15 v pvcc and pvccg power-on-reset threshold ppor r v cc rising 4.35 4.5 v ppor f v cc falling 4 4.15 v system and references system accuracy crtz no load; cl osed loop, active mode range vid = 0.75v to 1.52v -0.5 +0.5 % vid = 0.5v to 0.745v -8 +8 mv vid = 0.25v to 0.495v -15 +15 mv irtz no load; closed loop, active mode range vid = 0.75v to 1.52v -0.8 +0.8 % vid = 0.5v to 0.745v -10 +10 mv vid = 0.25v to 0.495v -18 +18 mv internal v boot crtz 1.0945 1.100 1.1055 v irtz 1.0912 1.1 1.1088 v
isl6363 9 fn6898.1 september 5, 2013 maximum output voltage v cc_core(max) vid = [11111111] 1.52 v minimum output voltage v cc_core(min) vid = [00000001] 0.25 v maximum output voltage with offset v cc_core(max) + offset register 33h = 7fh, vid = ffh 2.155 v channel frequency nominal channel frequency f sw(nom) r fset = 8.06k , 3-channel operation, v comp =1.1v 280 300 320 khz minimum adjustment range 200 khz maximum adjustment range 500 amplifiers current-sense amplifier input offset i fb = 0a -0.313 +0.313 mv error amp dc gain a v0 90 db error amp gain-bandwidth product gbw c l = 20pf 18 mhz isen imbalance voltage maximum of isens - minimum of isens 1.1 mv input bias current 20 na power-good and protection monitors pgood low voltage v ol i pgood = 4ma 0.15 0.4 v pgood leakage current i oh pgood = 3.3v 1 a pgood delay tpgd 3.8 ms alert# low resistance 7 13 ? vr_hot# low resistance 7 13 ? alert# leakage current 1 a vr_hot# leakage current 1 a gate drive switching time ugate rise time t rugate; v pvcc /v pvccg = 12v, 3nf load, 10% to 90% 26 ns lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% 18 ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% 18 ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% 12 ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive 10 ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive 10 ns gate drive resistance upper drive source resistance v pvcc = 12v, 15ma source current 2.0 w upper drive sink resistance v pvcc = 12v, 15ma sink current 1.35 w lower drive source resistance v pvcc = 12v, 15ma source current 1.35 w lower drive sink resistance v pvcc = 12v, 15ma sink current 0.90 w bootstrap diode forward voltage v f pvcc = 12v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a electrical specifications operating conditions: vcc = 5v, pvcc = 12v, pvccg = 12v, t a = 0c to +70c, (commercial) or -40c to +85c (industrial), f sw = 300khz, unless otherwise noted. boldface limits apply over the operating te mperature range, 0c to +70c (commercial) or -40c to +85c (industrial). (continu ed) parameter symbol test conditions min (note 6) typ max (note 6) units
isl6363 10 fn6898.1 september 5, 2013 protection overvoltage threshold ov h vsen rising above setpoint for >1s 116 232 mv current imbalance threshold one isen above another isen for >1.2ms 9 mv vr1 overcurrent threshold 4, 3, 2, 1-phase configuration ps0 mode 50 60 71 a 4-phase configuration, drop to 2-phase in ps1 mode 30 a 4-phase configuration, drop to 1-phase in ps2/3 mode 16 20 26 a 3-phase configuration, drop to 2-phase in ps1 40 a 3-phase configuration, dr op to 1-phase in ps2/3 16 20 26 a 2-phase configuration, drop to 1-phase in ps1/2/3 mode 30 a vr2 overcurrent threshold all modes of operation 50 60 71 a logic thresholds vr_on input low v il 0.3 v vr_on input high v ih 0.7 v pwm pwm output low v 0l sinking 5ma 1.0 v pwm output high (note 6) v 0h sourcing 5ma 3.5 4.2 v pwm tri-state leakage pwm = 2.5v 2 a thermal monitor ntc source current ntc = 1.3v 58 60 63 a vr_hot# trip voltage (vr1 and vr2) falling 0.86 0.873 0.89 v vr_hot# reset voltage (vr1 and vr2) rising 0.905 0.929 0.935 v therm_alert trip voltage (vr1 and vr2) falling 0.9 0.913 0.93 v therm_alert reset voltage (vr1 and vr2) rising 0.945 0.961 0.975 v current monitor imon output current (vr1 and vr2) isum- pin current = 25a 147 150 154 a iccmax_alert trip voltage (vr1 and vr2) rising 2.61 2.66 2.695 v iccmax_alert reset voltage (vr1 and vr2) falling 2.585 2.62 2.650 v inputs vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v 18 35 a sclk, sda leakage vr_on = 0v, sclk and sda = 0v and 1v -1 1 a vr_on = 1v, sclk and sda = 1v -5 1 a vr_on = 1v, sclk and sda = 0v -85 -60 -30 a slew rate (for vid change) fast slew rate 10 mv/s slow slew rate 2.5 mv/s note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: vcc = 5v, pvcc = 12v, pvccg = 12v, t a = 0c to +70c, (commercial) or -40c to +85c (industrial), f sw = 300khz, unless otherwise noted. boldface limits apply over the operating te mperature range, 0c to +70c (commercial) or -40c to +85c (industrial). (continu ed) parameter symbol test conditions min (note 6) typ max (note 6) units
isl6363 11 fn6898.1 september 5, 2013 gate driver timing diagram theory of operation multiphase r3 modulator the isl6363 is a multiphase regulator implementing intel?s? vr12? protocol. it has two voltage regulators, vr1 and vr2, on one chip. vr1 can be programmed for 1, 2, 3, or 4-phase operation, and vr2 is dedicate d for 1-phase operation. the following description is based on vr1, but also applies to vr2 because the same architecture is implemented. the isl6363 uses intersil?s patented r3 (robust ripple regulator) modulator. the r3 modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 3 conceptually shows the multiphase r3 modulator circuit, and figure 4 shows the operation principles. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between the two pins. this voltage window is called vw window in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the slave circuits. if vr1 is in 4-phase mode, the master clock signal will be distributed to th e four phases, and the clock1~4 signals will be 90 out-of-phase. if vr1 is in 3-phase mode, the master clock signal will be distributed to the three phases, and the clock1~3 signals will be 120 out- of-phase. if vr1 is in 2-phase mode, the master clock signal will be distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of-phase. if vr1 is in 1-phase mode, the master clock signal will be distributed to phase 1 only and be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr figure 3. r3 modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3
isl6363 12 fn6898.1 september 5, 2013 since the controller works with v crs , which are large-amplitude and noise-free synthesized signals, it achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the isl6363 uses an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. figure 5 shows the operation principles during load insertion response. the comp voltage rises during load insertion, generating the master clock signal more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency, which allows for higher control lo op bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, the comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the comp voltage falls, reducing the current pwm pulse width. this kind of behavior gives the isl6363 excellent response speed. the fact that all the phases share the same vw window voltage also ensures excellent dynamic current balance among phases. diode emulation and period stretching of the isl6363 can operate in diode emulation (de) mode to improve light load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and does not allow reverse current, emulating a diode. as figu re 6 shows, when lgate is on, the low-side mosfet carries curren t, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the isl6363 monitors the current through monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enough, as figure 6 shows, the inductor current will reach and stay at ze ro before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 4. r3 modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw figure 5. r3 modulator operation principles in load insertion response comp vcrm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw ugate phase il lgate figure 6. diode emulation
isl6363 13 fn6898.1 september 5, 2013 figure 7 shows the operation principle in diode emulation mode at light load. the load gets incremen tally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triangle the same in the three cases. the isl6363 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light load efficiency. start-up timing with the controller's v cc voltage above the por threshold, the start-up sequence begins when vr_on exceeds the logic high threshold. figure 8 shows the typical start-up timing of vr1 and vr2. the isl6363 uses digital so ft-start to ramp-up dac to the voltage programmed by the setvid command. pgood is asserted high and alert# is asserted lo w at the end of the ramp-up. similar results occur if vr_on is tied to vcc, with the soft-start sequence starting 800s after vcc crosses the por threshold. voltage regulation and load line implementation after the start sequence, the isl6 363 regulates the output voltage to the value set by the vid information per table 1. the isl6363 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.52v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 7. period stretching vcc vr_on dac 3.8ms 2.5mv/s vid slew rate vid command voltage pgood alert# ?... figure 8. vr1 soft-start waveforms table 1. vid table vid hex v o (v) 765 43210 0 0 0 0 0 0 0 0 0 0 0.00000 0 0 0 0 0 0 0 1 0 1 0.25000 0 0 0 0 0 0 1 0 0 2 0.25500 0 0 0 0 0 0 1 1 0 3 0.26000 0 0 0 0 0 1 0 0 0 4 0.26500 0 0 0 0 0 1 0 1 0 5 0.27000 0 0 0 0 0 1 1 0 0 6 0.27500 0 0 0 0 0 1 1 1 0 7 0.28000 0 0 0 0 1 0 0 0 0 8 0.28500 0 0 0 0 1 0 0 1 0 9 0.29000 0 0 0 0 1 0 1 0 0 a 0.29500 0 0 0 0 1 0 1 1 0 b 0.30000 0 0 0 0 1 1 0 0 0 c 0.30500 000 011010d0.31000 0 0 0 0 1 1 1 0 0 e 0.31500 0 0 0 0 1 1 1 1 0 f 0.32000 0 0 0 1 0 0 0 0 1 0 0.32500 0 0 0 1 0 0 0 1 1 1 0.33000 0 0 0 1 0 0 1 0 1 2 0.33500 0 0 0 1 0 0 1 1 1 3 0.34000 0 0 0 1 0 1 0 0 1 4 0.34500 0 0 0 1 0 1 0 1 1 5 0.35000 0 0 0 1 0 1 1 0 1 6 0.35500 0 0 0 1 0 1 1 1 1 7 0.36000 0 0 0 1 1 0 0 0 1 8 0.36500 000 11001190.37000 000 110101a0.37500 0 0 0 1 1 0 1 1 1 b 0.38000 0 0 0 1 1 1 0 0 1 c 0.38500 0 0 0 1 1 1 0 1 1 d 0.39000 0 0 0 1 1 1 1 0 1 e 0.39500 0 0 0 1 1 1 1 1 1 f 0.40000 0 0 1 0 0 0 0 0 2 0 0.40500
isl6363 14 fn6898.1 september 5, 2013 001 00001210.41000 0 0 1 0 0 0 1 0 2 2 0.41500 0 0 1 0 0 0 1 1 2 3 0.42000 0 0 1 0 0 1 0 0 2 4 0.42500 0 0 1 0 0 1 0 1 2 5 0.43000 0 0 1 0 0 1 1 0 2 6 0.43500 0 0 1 0 0 1 1 1 2 7 0.44000 0 0 1 0 1 0 0 0 2 8 0.44500 0 0 1 0 1 0 0 1 2 9 0.45000 0 0 1 0 1 0 1 0 2 a 0.45500 0 0 1 0 1 0 1 1 2 b 0.46000 0 0 1 0 1 1 0 0 2 c 0.46500 0 0 1 0 1 1 0 1 2 d 0.47000 0 0 1 0 1 1 1 0 2 e 0.47500 0 0 1 0 1 1 1 1 2 f 0.48000 0 0 1 1 0 0 0 0 3 0 0.48500 0 0 1 1 0 0 0 1 3 1 0.49000 0 0 1 1 0 0 1 0 3 2 0.49500 0 0 1 1 0 0 1 1 3 3 0.50000 0 0 1 1 0 1 0 0 3 4 0.50500 001 10101350.51000 001 10110360.51500 0 0 1 1 0 1 1 1 3 7 0.52000 0 0 1 1 1 0 0 0 3 8 0.52500 0 0 1 1 1 0 0 1 3 9 0.53000 0 0 1 1 1 0 1 0 3 a 0.53500 0 0 1 1 1 0 1 1 3 b 0.54000 0 0 1 1 1 1 0 0 3 c 0.54500 0 0 1 1 1 1 0 1 3 d 0.55000 0 0 1 1 1 1 1 0 3 e 0.55500 0 0 1 1 1 1 1 1 3 f 0.56000 0 1 0 0 0 0 0 0 4 0 0.56500 010 00001410.57000 010 00010420.57500 0 1 0 0 0 0 1 1 4 3 0.58000 0 1 0 0 0 1 0 0 4 4 0.58500 0 1 0 0 0 1 0 1 4 5 0.59000 0 1 0 0 0 1 1 0 4 6 0.59500 0 1 0 0 0 1 1 1 4 7 0.60000 0 1 0 0 1 0 0 0 4 8 0.60500 table 1. vid table (continued) vid hex v o (v) 765 43210 010 01001490.61000 0 1 0 0 1 0 1 0 4 a 0.61500 0 1 0 0 1 0 1 1 4 b 0.62000 0 1 0 0 1 1 0 0 4 c 0.62500 0 1 0 0 1 1 0 1 4 d 0.63000 0 1 0 0 1 1 1 0 4 e 0.63500 0 1 0 0 1 1 1 1 4 f 0.64000 0 1 0 1 0 0 0 0 5 0 0.64500 0 1 0 1 0 0 0 1 5 1 0.65000 0 1 0 1 0 0 1 0 5 2 0.65500 0 1 0 1 0 0 1 1 5 3 0.66000 0 1 0 1 0 1 0 0 5 4 0.66500 0 1 0 1 0 1 0 1 5 5 0.67000 0 1 0 1 0 1 1 0 5 6 0.67500 0 1 0 1 0 1 1 1 5 7 0.68000 0 1 0 1 1 0 0 0 5 8 0.68500 0 1 0 1 1 0 0 1 5 9 0.69000 0 1 0 1 1 0 1 0 5 a 0.69500 0 1 0 1 1 0 1 1 5 b 0.70000 0 1 0 1 1 1 0 0 5 c 0.70500 010 111015d0.71000 0 1 0 1 1 1 1 0 5 e 0.71500 0 1 0 1 1 1 1 1 5 f 0.72000 0 1 1 0 0 0 0 0 6 0 0.72500 0 1 1 0 0 0 0 1 6 1 0.73000 0 1 1 0 0 0 1 0 6 2 0.73500 0 1 1 0 0 0 1 1 6 3 0.74000 0 1 1 0 0 1 0 0 6 4 0.74500 0 1 1 0 0 1 0 1 6 5 0.75000 0 1 1 0 0 1 1 0 6 6 0.75500 0 1 1 0 0 1 1 1 6 7 0.76000 0 1 1 0 1 0 0 0 6 8 0.76500 0 1 1 0 1 0 0 1 6 9 0.77000 0 1 1 0 1 0 1 0 6 a 0.77500 0 1 1 0 1 0 1 1 6 b 0.78000 0 1 1 0 1 1 0 0 6 c 0.78500 0 1 1 0 1 1 0 1 6 d 0.79000 0 1 1 0 1 1 1 0 6 e 0.79500 0 1 1 0 1 1 1 1 6 f 0.80000 0 1 1 1 0 0 0 0 7 0 0.80500 table 1. vid table (continued) vid hex v o (v) 765 43210
isl6363 15 fn6898.1 september 5, 2013 011 10001710.81000 0 1 1 1 0 0 1 0 7 2 0.81500 0 1 1 1 0 0 1 1 7 3 0.82000 0 1 1 1 0 1 0 0 7 4 0.82500 0 1 1 1 0 1 0 1 7 5 0.83000 0 1 1 1 0 1 1 0 7 6 0.83500 0 1 1 1 0 1 1 1 7 7 0.84000 0 1 1 1 1 0 0 0 7 8 0.84500 0 1 1 1 1 0 0 1 7 9 0.85000 0 1 1 1 1 0 1 0 7 a 0.85500 0 1 1 1 1 0 1 1 7 b 0.86000 0 1 1 1 1 1 0 0 7 c 0.86500 0 1 1 1 1 1 0 1 7 d 0.87000 0 1 1 1 1 1 1 0 7 e 0.87500 0 1 1 1 1 1 1 1 7 f 0.88000 1 0 0 0 0 0 0 0 8 0 0.88500 1 0 0 0 0 0 0 1 8 1 0.89000 1 0 0 0 0 0 1 0 8 2 0.89500 1 0 0 0 0 0 1 1 8 3 0.90000 1 0 0 0 0 1 0 0 8 4 0.90500 100 00101850.91000 1 0 0 0 0 1 1 0 8 6 0.91500 1 0 0 0 0 1 1 1 8 7 0.92000 1 0 0 0 1 0 0 0 8 8 0.92500 1 0 0 0 1 0 0 1 8 9 0.93000 1 0 0 0 1 0 1 0 8 a 0.93500 1 0 0 0 1 0 1 1 8 b 0.94000 1 0 0 0 1 1 0 0 8 c 0.94500 1 0 0 0 1 1 0 1 8 d 0.95000 1 0 0 0 1 1 1 0 8 e 0.95500 1 0 0 0 1 1 1 1 8 f 0.96000 1 0 0 1 0 0 0 0 9 0 0.96500 1 0 0 1 0 0 0 1 9 1 0.97000 1 0 0 1 0 0 1 0 9 2 0.97500 1 0 0 1 0 0 1 1 9 3 0.98000 1 0 0 1 0 1 0 0 9 4 0.98500 1 0 0 1 0 1 0 1 9 5 0.99000 1 0 0 1 0 1 1 0 9 6 0.99500 1 0 0 1 0 1 1 1 9 7 1.00000 1 0 0 1 1 0 0 0 9 8 1.00500 table 1. vid table (continued) vid hex v o (v) 765 43210 100 11001991.01000 1 0 0 1 1 0 1 0 9 a 1.01500 1 0 0 1 1 0 1 1 9 b 1.02000 1 0 0 1 1 1 0 0 9 c 1.02500 1 0 0 1 1 1 0 1 9 d 1.03000 1 0 0 1 1 1 1 0 9 e 1.03500 1 0 0 1 1 1 1 1 9 f 1.04000 1 0 1 0 0 0 0 0 a 0 1.04500 1 0 1 0 0 0 0 1 a 1 1.05000 1 0 1 0 0 0 1 0 a 2 1.05500 1 0 1 0 0 0 1 1 a 3 1.06000 1 0 1 0 0 1 0 0 a 4 1.06500 1 0 1 0 0 1 0 1 a 5 1.07000 1 0 1 0 0 1 1 0 a 6 1.07500 1 0 1 0 0 1 1 1 a 7 1.08000 1 0 1 0 1 0 0 0 a 8 1.08500 1 0 1 0 1 0 0 1 a 9 1.09000 1 0 1 0 1 0 1 0 a a 1.09500 1 0 1 0 1 0 1 1 a b 1.10000 1 0 1 0 1 1 0 0 a c 1.10500 101 01101ad1.11000 1 0 1 0 1 1 1 0 a e 1.11500 1 0 1 0 1 1 1 1 a f 1.12000 1 0 1 1 0 0 0 0 b 0 1.12500 1 0 1 1 0 0 0 1 b 1 1.13000 1 0 1 1 0 0 1 0 b 2 1.13500 1 0 1 1 0 0 1 1 b 3 1.14000 1 0 1 1 0 1 0 0 b 4 1.14500 1 0 1 1 0 1 0 1 b 5 1.15000 1 0 1 1 0 1 1 0 b 6 1.15500 1 0 1 1 0 1 1 1 b 7 1.16000 1 0 1 1 1 0 0 0 b 8 1.16500 1 0 1 1 1 0 0 1 b 9 1.17000 1 0 1 1 1 0 1 0 b a 1.17500 1 0 1 1 1 0 1 1 b b 1.18000 1 0 1 1 1 1 0 0 b c 1.18500 1 0 1 1 1 1 0 1 b d 1.19000 1 0 1 1 1 1 1 0 b e 1.19500 1 0 1 1 1 1 1 1 b f 1.20000 1 1 0 0 0 0 0 0 c 0 1.20500 table 1. vid table (continued) vid hex v o (v) 765 43210
isl6363 16 fn6898.1 september 5, 2013 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the isl6363 can sense the inductor current through the intrin sic dc resistance (dcr) of the inductors as shown in figure 16 or through resistors in series with the inductors as shown in figure 22. in both methods, capacitor c n voltage represents the inductor total currents. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitor and overcurrent protection. figure 9 shows the load line im plementation. the isl6363 drives a current source i droop out of the fb pin, described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding, thus sustaining the load line accuracy with reduced cost. 110 00001c11.21000 1 1 0 0 0 0 1 0 c 2 1.21500 1 1 0 0 0 0 1 1 c 3 1.22000 1 1 0 0 0 1 0 0 c 4 1.22500 1 1 0 0 0 1 0 1 c 5 1.23000 1 1 0 0 0 1 1 0 c 6 1.23500 1 1 0 0 0 1 1 1 c 7 1.24000 1 1 0 0 1 0 0 0 c 8 1.24500 1 1 0 0 1 0 0 1 c 9 1.25000 1 1 0 0 1 0 1 0 c a 1.25500 1 1 0 0 1 0 1 1 c b 1.26000 1 1 0 0 1 1 0 0 c c 1.26500 1 1 0 0 1 1 0 1 c d 1.27000 1 1 0 0 1 1 1 0 c e 1.27500 1 1 0 0 1 1 1 1 c f 1.28000 1 1 0 1 0 0 0 0 d 0 1.28500 1 1 0 1 0 0 0 1 d 1 1.29000 1 1 0 1 0 0 1 0 d 2 1.29500 1 1 0 1 0 0 1 1 d 3 1.30000 1 1 0 1 0 1 0 0 d 4 1.30500 110 10101d51.31000 1 1 0 1 0 1 1 0 d 6 1.31500 1 1 0 1 0 1 1 1 d 7 1.32000 1 1 0 1 1 0 0 0 d 8 1.32500 1 1 0 1 1 0 0 1 d 9 1.33000 1 1 0 1 1 0 1 0 d a 1.33500 1 1 0 1 1 0 1 1 d b 1.34000 1 1 0 1 1 1 0 0 d c 1.34500 1 1 0 1 1 1 0 1 d d 1.35000 1 1 0 1 1 1 1 0 d e 1.35500 1 1 0 1 1 1 1 1 d f 1.36000 1 1 1 0 0 0 0 0 e 0 1.36500 1 1 1 0 0 0 0 1 e 1 1.37000 1 1 1 0 0 0 1 0 e 2 1.37500 1 1 1 0 0 0 1 1 e 3 1.38000 1 1 1 0 0 1 0 0 e 4 1.38500 1 1 1 0 0 1 0 1 e 5 1.39000 1 1 1 0 0 1 1 0 e 6 1.39500 1 1 1 0 0 1 1 1 e 7 1.40000 1 1 1 0 1 0 0 0 e 8 1.40500 table 1. vid table (continued) vid hex v o (v) 765 43210 111 01001e91.41000 1 1 1 0 1 0 1 0 e a 1.41500 1 1 1 0 1 0 1 1 e b 1.42000 1 1 1 0 1 1 0 0 e c 1.42500 1 1 1 0 1 1 0 1 e d 1.43000 1 1 1 0 1 1 1 0 e e 1.43500 1 1 1 0 1 1 1 1 e f 1.44000 1 1 1 1 0 0 0 0 f 0 1.44500 1 1 1 1 0 0 0 1 f 1 1.45000 1 1 1 1 0 0 1 0 f 2 1.45500 1 1 1 1 0 0 1 1 f 3 1.46000 1 1 1 1 0 1 0 0 f 4 1.46500 1 1 1 1 0 1 0 1 f 5 1.47000 1 1 1 1 0 1 1 0 f 6 1.47500 1 1 1 1 0 1 1 1 f 7 1.48000 1 1 1 1 1 0 0 0 f 8 1.48500 1 1 1 1 1 0 0 1 f 9 1.49000 1 1 1 1 1 0 1 0 f a 1.49500 1 1 1 1 1 0 1 1 f b 1.50000 1 1 1 1 1 1 0 0 f c 1.50500 111 11101fd1.51000 1 1 1 1 1 1 1 0 f e 1.51500 1 1 1 1 1 1 1 1 f f 1.52000 table 1. vid table (continued) vid hex v o (v) 765 43210 i droop 2xv cn r i ---------------- = (eq. 1)
isl6363 17 fn6898.1 september 5, 2013 i droop flows through resistor r droop and creates a voltage drop as shown in equation 2. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential voltage sensing figure 9 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and add it to the dac output. the error amplifier regulates the invertin g and the non-inverting input voltages to be equal as shown in equation 3: rewriting equation 3 and substitution of equation 2 gives equation 4 is the exact equa tion required for load line implementation. the vcc sense and vss sense signals come from the processor die. the feedback will be open circuit in the absence of the processor. as figure 9 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without a processor installed. phase current balancing the isl6363 monitors individual phase average current by monitoring the isen1, isen2, isen3, and is en4 voltages. figure 10 shows the current balancing circuit recommended for isl6363 for a 3-phase configuration as an example. each phase node voltage is averaged by a low-pass filter consisting of r isen and c isen , and presented to the corresponding isen pin. r isen should be routed to the inductor phase-node pad in order to eliminate the effect of phase node parasitic pcb dcr. equations 5 through 7 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are inductor dcr; r pcb1 , r pcb2 and r pcb3 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. the isl6363 will adjust the phase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus, to achieve i l1 =i l2 =i l3 , when there are r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . using the same components for l1, l2 and l3 will provide a good match of r dcr1 , r dcr2 and r dcr3 . board layout will determine r pcb1 , r pcb2 and r pcb3 . it is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 =r pcb3 . sometimes it is difficult to implement symmetrical layout. for the circuit shown in figure 10, asymmetric layout causes different r pcb1 , r pcb2 and r pcb3 , thus current imbalance. figure 11 shows a differential-sensing current balancing circuit recommended for the isl6363. the current sensing traces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of x 1 e/a dac rdroop idroop vdac vdroop fb comp vcc sense vss sense vid rtn vss internal to ic ?catch? resistor ?catch? resistor vr local vo figure 9. differential sensing and load line implementation v droop r droop i droop = (eq. 2) vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop ? = (eq. 4) v isen1 r dcr1 r pcb1 + () i l1 = (eq. 5) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 6) v isen3 r dcr3 r pcb3 + () i l3 = (eq. 7) internal to ic v o isen3 l3 risen cisen isen2 risen cisen isen1 risen cisen l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 figure 10. current balancing circuit internal to ic v o isen3 l3 risen cisen isen2 risen cisen isen1 risen cisen l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 risen risen risen risen risen risen v3p v3n v2p v2n v1p v1n figure 11. differential-sensin g current balancing circuit
isl6363 18 fn6898.1 september 5, 2013 three sources: its own phase indu ctor phase-node pad, and the other two phases inductor output side pads. equations 8 thru 10 give the isen pin voltages: the isl6363 will make v isen1 = v isen2 = v isen3 as shown in equations 11 and 12: rewriting equation 11 gives equation 13: and rewriting equation 12 gives equation 14: combining equations 13 and 14 gives: therefore: current balancing (i l1 =i l2 =i l3 ) will be achieved when there is r dcr1 =r dcr2 =r dcr3 . r pcb1 , r pcb2 and r pcb3 will not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, the r3 modulator can naturally achieve excellent current balancing during steady state and dynamic operations. figure 12 shows current balancing performance of the evaluation board with a load tr ansient of 12a/51a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at low rep rate, but cannot keep up when the rep rate gets into the hundred-khz range, where it?s out of the cont rol loop bandwidth. the controller achieves excellent current bala ncing in all cases installed. ccm switching frequency the r fset resistor between the comp and the vw pins sets the vw windows size, therefore sets the switching frequency. when the isl6363 is in continuous conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r3 modulator. as explained in the multiphase r3 modulator section on page 11, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. on the other hand, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load , etc., changes. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. equation 17 gives an estimate of the frequency-setting resistor r fset value. 8k r fset gives approximately 300khz switching frequency. lower resistance gives higher switching frequency. v isen1 v 1p v 2n v 3n ++ = (eq. 8) v isen2 v 1n v 2p v 3n ++ = (eq. 9) v isen3 v 1n v 2n v 3p ++ = (eq. 10) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 11) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 12) v 1p v 1n ? v 2p v 2n ? = (eq. 13) v 2p v 2n ? v 3p v 3n ? = (eq. 14) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 15) r dcr1 i l1 r dcr2 i l2 r dcr3 i l3 == (eq. 16) r fset k () period s () 0.29 ? () 2.65 = (eq. 17) figure 12. current balancing during dynamic operation. ch1: il1, ch2: i load , ch3: il2, ch4: il3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz
isl6363 19 fn6898.1 september 5, 2013 modes of operation vr1 can be configured for 4, 3, 2 or 1-phase operation. table 2 shows vr1 configurations and operational modes, programmed by the pwm4, pwm3 pins and th e isen2 pin status, and the ps command. for 3-phase configuration, tie the pwm4 pin to 5v. in this configuration, phases 1, 2 and 3 are active. for 2-phase configuration, tie the pwm4 and pwm3 pin to 5v. in this configuration, phases 1 and 2 are active. for 1-phase configuration, tie the pwm4, pwm3 and the isen2 pin to 5v. in this configuration, only phase 1 is active. in 4-phase configurat ion, vr1 operates in 4-phase ccm in ps0 mode. it enters 2-phase ccm operation in ps1 mode. it enters 1-phase de operation in ps2 and ps3 modes. in 3-phase configurat ion, vr1 operates in 3-phase ccm in ps0 mode. it enters 2-phase ccm operation in ps1 mode. it enters 1-phase de operation in ps2 and ps3 modes. in 2-phase configurat ion, vr1 operates in 2-phase ccm in ps0 and ps1 mode. it enters 1-phase de mode in ps2 and ps3 modes. in 1-phase configurat ion, vr1 operates in 1-phase ccm in ps0 and ps1, and enters 1-phase de mode in ps2 and ps3. table 3 shows vr2 operational mo des, programmed by the ps command. vr2 operates in 1-phase ccm in ps0 and ps1, and enters 1-phase de mode in ps2 and ps3 mode. vr2 can be disabled completely by tying isumng to 5v, and all communication to vr2 will be blocked. dynamic operation vr1 and vr2 behave the same during dynamic operation. the controller responds to vid changes by slewing to the new voltage at a slew rate indicated in the setvid command. there are three setvid slew rates, namely setvid_fast, setvid_slow and setvid_decay. setvid_fast command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 10mv/s slew rate. setvid_slow command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 2.5mv/s slew rate. setvid_decay command prompts the controller to enter de mode. the output voltage will decay down to the new vid value at a slew rate determined by the load. if the voltage decay rate is too fast, the controller will limit the voltage slew rate at setvid_slow slew rate. alert# will be asserted low at the end of setvid_fast and setvid_slow vid transitions. figure 13 shows setvid deca y pre-emptive behavior. the controller receives a setvid_d ecay command at t1. the vr enters de mode and the output voltage v o decays down slowly. at t2, before v o reaches the intended vid target of the setvid_decay command, the controller receives a setvid_fast (or setvid_slow) command to go to a voltage higher th an the actual v o . the controller will turn around immediately and slew v o to the new target voltage at the slew rate specified by the setvid command. at t3, v o reaches the new target voltage and the controller asserts the alert# signal. the r3 modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. table 2. vr1 modes of operation pwm4 pwm3 isen2 config. ps mode ocp threshold (a) to ext driver to ext driver to power stage 4-phase cpu vr config. 0 4-ph ccm 60 1 2-ph ccm 30 21-ph de 20 3 tie to 5v vcc 3-phase cpu vr config. 0 3-ph ccm 60 1 2-ph ccm 40 21-ph de 20 3 tie to 5v vcc 2-phase cpu vr config. 0 2-ph ccm 60 1 2-ph ccm 60 21-ph de 30 3 tie to 5v vcc 1-phase cpu vr config. 0 1-ph ccm 60 1 21-ph de 3 table 3. vr2 modes of operation ps mode ocp threshold 0 1-phase ccm 60a 1 21-phase de 3 figure 13. setvid decay pre-emptive behavior v o setvid_decay setvid_fast/slow t_alert vid alert# t1 t2 t3
isl6363 20 fn6898.1 september 5, 2013 vr_hot#/alert# behavior the controller drives 60a curren t source out of the ntc pin and the ntcg pin alternatively at 1khz frequency with 50% duty cycle. the current source flows through the respective ntc resistor networks on the pins and creates voltages that are monitored by the controller through an a/d converter (adc) to generate the tzone value. table 4 shows the programming table for tzone. the user needs to scale the ntc and the ntcg network resistance such that it generates the ntc (and ntcg) pin voltage that corresponds to the left-most column. do not use any capacitor to filter the voltage. figure 14 shows how the ntc and the ntcg network should be designed to get correct vr_hot#/alert# behavior when the system temperature rises and falls , manifested as the ntc and the ntcg pin voltage falls and rises. the series of events are: 1. the temperature rises so the ntc pin (or the ntcg pin) voltage drops. tzone value changes accordingly. 2. the temperature crosses the threshold where the tzone register bit 6 changes from 0 to 1. 3. the controller changes status_1 register bit 1 from 0 to 1. 4. the controller asserts alert#. 5. the cpu reads status_1 register value to know that the alert assertion is due to tzone register bit 6 flipping. 6. the controller clears alert#. 7. the temperature continues rising. 8. the temperature crosses the threshold where the tzone register bit 7 changes from 0 to 1. 9. the controller asserts the vr_hot# signal. the cpu throttles back and the system temperature starts dropping eventually. 10. the temperature crosses the threshold where the tzone register bit 6 changes from 1 to 0. this threshold is 1 adc step lower than the one when vr_hot# gets asserted, to provide 3% hysteresis. 11. the controllers de-assert the vr_hot# signal. 12. the temperature crosses the threshold where the tzone register bit 5 changes from 1 to 0. this threshold is 1 adc step lower than the one when alert# gets asserted during the temperature rise to provide 3% hysteresis. 13. the controller changes status_1 register bit 1 from 1 to 0. 14. the controller asserts alert#. 15. the cpu reads status_1 register value to know that the alert assertion is due to tzone register bit 5 flipping. 16. the controller clears alert#. protection functions vr1 and vr2 both provide overcurrent, current-balance and overvoltage fault protections. the controller also provides over-temperature protection. the fo llowing discussion is based on vr1 and also applies to vr2. the controller determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold as table 2 shows. it declares ocp when i droop is above the threshold for 120s. for overcurrent conditions above 1.5x the ocp level, the pwm outputs will immediately shut off and pgood will go low to maximize protection. this protec tion is also referred to as way-overcurrent protection or fast-overcurrent protection, for short-circuit protections. the controller monitors the isen pin voltages to determine current-balance protection. if the isen pin voltage difference is greater than 9mv for 1ms, the controller will declare a fault and latch off. the controller takes the same actions for all of the above fault protections: de-assertion of pgoo d and turn-off of the high-side and low-side power mosfets. any residual inductor current will decay through the mosfet body diodes. the controller will declare an over voltage fault and de-assert pgood if the output voltage exceeds the vid set value by +200mv. the isl6363 will immediately declare an ov fault, de-assert pgood, and turn on the low-side powe r mosfets. the low-side power mosfets remain on until the output voltage is pulled down below the vid set value when all power mosfets are turned off. if the output voltage rises above the vid set value +200mv again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. table 4. tzone table vntc (v) tmax (%) tzone 0.84 >100 ffh 0.88 100 ffh 0.92 97 7fh 0.96 94 3fh 1.00 91 1fh 1.04 88 0fh 1.08 85 07h 1.12 82 03h 1.16 79 01h 1.2 76 01h >1.2 <76 00h 1 bit 6 =1 bit 7 =1 bit 5 =1 temp zone register 0001 1111 0011 1111 0 1 11 1111 1 111 1111 0 1 11 1111 0011 1111 0001 1111 status 1 register = ?001? = ?0 1 1? = ?0 0 1? temp zone 7 2 3 5 svid alert# vr_hot# 4 gerreg status1 8 6 9 10 11 1111 1111 0111 1111 0011 1111 0001 1111 12 13 15 gerreg status1 14 16 3% hysteresis vr temperature figure 14. vr_hot#/alert# behavior
isl6363 21 fn6898.1 september 5, 2013 all the above fault conditions can be reset by bringing vr_on low or by bringing vcc below the por threshold. when vr_on and vcc return to their high operatin g levels, a soft-start will occur table 5 summarizes the fault protections. current monitor the isl6363 provides the current mo nitor function for both vrs. imon pin reports vr1 inductor current and imong pins reports vr2 inductor current. since they are designed following the same principle, the following discussion will be only based on the imon pin but also applies to the imong pin. the imon pin outputs a high-speed analog current source that is 3 times of the droop current flow ing out of the fb pin. thus becoming equation 18: as the ?simplified application circuit? on page 6 shows, a resistor r imon is connected to the imon pin to convert the imon pin current to voltage. a capacitor can be paralleled with r imon to filter the voltage information. the imon pin voltage range is 0v to 2.7v. the controller monitors the imon pin voltage and considers that vr1 has reached iccmax on imon pin voltage is 2.7v. psicomp function figure 15 shows the psicomp function. a switch turns on to short the fb and the psicomp pins when the controller is in ps2 mode. the rc network c2.2 and r3.2 is connected in parallel with r1 and c2/r3 compensation network in ps2/3 mode. this additional rc network increases the high frequency content of the signal passing from the output voltage to the comp pin which will improve transient response in ps2/3 mode of operation. when the psicomp switch is off, c2.2 and r3.2 are disconnected from the fb pin. however, the controller still actively drives the psicomp pin to allow for smooth transitions between modes of operation. the psicomp function ensures ex cellent transient response in both ps0, ps1 and ps2/3 modes of operation. if the psicomp function is not needed c2.2 and r3.2 can be disconnected. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comp arator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the low- side mosfet turns off, it will flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it will flow through the high-side mosfet body diode, causing the ph ase node to have a spike until it decays to zero. the controlle r continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator threshold voltage accordingly in iterative steps, such that the low-side mosfet body diode conducts for approximately 40ns to minimize the body diode-related loss. supported data and configuration registers the controller supports the fo llowing data and configuration registers. table 5. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vcc toggle phase current unbalance 1ms way-overcurrent (1.5xoc) immediately overvoltage +200mv pgood latched low. actively pulls the output voltage to below vid value, then tri-state. i imon 3i droop = (eq. 18) table 6. supported data and configuration registers index register name description default value 00h vendor id uniquely identifies the vr vendor. assigned by intel. 12h 01h product id uniquely identifies the vr product. intersil assigns this number. 1fh 02h product revision uniquely identifies the revision of the vr control ic. intersil assigns this data. 05h protocol id identifies what revision of svid protocol the controller supports. 01h r1 e/a r3 c2 c1 r2 c3.1 fb comp vsen r1 e/a r3 c2 c1 r2 c3.1 fb comp vsen controller in ps0/1 mode controller in ps2/3 mode r3.2 c2.2 psicomp r3.2 c2.2 psicomp figure 15. psicomp function
isl6363 22 fn6898.1 september 5, 2013 key component selection inductor dcr current-sensing network figure 16 shows the inductor dcr current-sensing network for a 3-phase solution. an inductor cu rrent flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to a ccurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summ ing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature-compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the 06h capability identifies the svid vr capabilities and which of the optional telemetry registers are supported. 81h 10h status_1 data register read after alert# signal. indicating if a vr rail has settled, has reached vrhot condition or has reached icc max. 00h 11h status_2 data register showing status_2 communication. 00h 12h temperature zone data register showing temperature zones that have been entered. 00h 1ch status_2_ lastread this register contains a copy of the status_2 data that was last read with the getreg (status_2) command. 00h 21h icc max data register containing the icc max the platform supports, set at start-up by resistors rprog1 and rprog2. the platform design engineer programs this value during the design process. binary format in amps, i.e., 100a = 64h refer to table 7 22h temp max data register containing the temperature max the platform support, set at startup by resistor rprog2. the platform design engineer programs this value during the design process. binary format in c, i.e., +100c = 64h refer to table 8 24h sr-fast slew rate normal. the fastest slew rate the platform vr can sustain. binary format in mv/s. i.e., 0ah = 10mv/s. 0ah 25h sr-slow is 4x slower than normal. binary format in mv/s. i.e., 02h = 2.5mv/s 02h 26h v boot if programmed by the platform, the vr supports v boot voltage during start-up ramp. the vr will ramp to v boot and hold at v boot until it receives a new setvid command to move to a different voltage. 00h 30h vout max this register is programmed by the master and sets the maximum vid the vr will support. if a higher vid code is received, the vr will respond with ?not supported? acknowledge. fbh table 6. supported data and configuration registers (continued) index register name description default value 31h vid setting data register containing currently programmed vid voltage. vid data format. 00h 32h power state register containing the current programmed power state. 00h 33h voltage offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is a sign bit, 0 = positive margin, 1 = negative margin. remaining 7 bits are # vid steps for the margin. 00h = no margin, 01h = +1 vid step 02h = +2 vid steps 00h 34h multi vr config data register that configures multiple vrs behavior on the same svid bus. vr1: 00h vr2: 01h table 6. supported data and configuration registers (continued) index register name description default value cn rsum ro rntcs rntc rp dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn figure 16. dcr current-sensing network
isl6363 23 fn6898.1 september 5, 2013 current-sensing summing network. it is recommended to use 1 ~10 r o to create quality signals. since r o value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. the summed inductor current information is presented to the capacitor c n . equations 19 thru 23 describe the frequency-domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc values decreases as its temp erature decreases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represent the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltag e. it is recommended to have a higher ratio of v cn to the inductor dcr voltage, so the droop circuit has higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k , r p = 11k , r ntcs = 2.61k and r ntc = 10k (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output vo ltage reading imme diately; then record the output voltage read ing again when the board has reached the thermal steady state. a good ntc network can limit the output voltage drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient resp onse. transfer function a cs (s) has a pole w sns and a zero w l . one needs to match w l and w sns so a cs (s) is unity gain at all frequencies. by forcing w l equal to w sns and solving for the solution, equation 24 gives cn value. for example, given n = 3, r sum = 3.65k , r p = 11k , r ntcs =2.61k , r ntc = 10k , dcr = 0.88m and l = 0.36h, equation 24 gives c n = 0.406f. assuming the compensator design is correct, figure 17 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 18 shows the load transient response when c n is too small. v core will sag excessively upon load insertion and may create a system failure. figure 19 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. v cn s () r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 19) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - = (eq. 20) a cs s () 1 s l ------ + 1 s sns ------------ + ---------------------- = (eq. 21) l dcr l ----------- - = (eq. 22) sns 1 r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- c n ------------------------------------------------------ = (eq. 23) c n l r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- dcr ----------------------------------------------------------- - = (eq. 24) figure 17. desired load transient response waveforms o i v o figure 18. load transient response when c n is too small o i v o figure 19. load transient response when c n is too large o i v o
isl6363 24 fn6898.1 september 5, 2013 figure 20 shows the output volt age ring back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fashion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenom enon is not observed when the output capacitor have very low esr and esl, such as all ceramic capacitors. figure 21 shows two optional circ uits for reduction of the ring back. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 21 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional component to reduce the v o ring back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 18 explains, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning th e load transient response waveforms on an actual board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. resistor current-sensing network figure 22 shows the resistor current-sensing network for a 2-phase solution. each inductor has a series current-sensing resistor r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 25 thru 27 give v cn (s) expression transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value will not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k and c n = 5600pf. figure 20. output voltage ring back problem o i v o l i ring back figure 21. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional figure 22. resistor cu rrent-sensing network cn rsum ro dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn rsen rsen rsen v cn s () r sen n ------------ i o s () a rsen s () = (eq. 25) a rsen s () 1 1 s sns ------------ + ---------------------- = (eq. 26) rsen 1 r sum n -------------- c n --------------------------- = (eq. 27)
isl6363 25 fn6898.1 september 5, 2013 overcurrent protection refer to equation 1 on page 16 and figures 16, 20 and 22; resistor r i sets the droop current i droop . tables 2 (page 19) and 3 (page 19) show the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 60a for 3-phase solution. we will design i droop to be 40.9a at full load, so the ocp trip level is 1.5x of the full load current. for inductor dcr sensing, equation 28 gives the dc relationship of v cn (s) and i o (s). substitution of equation 28 into equation 1 gives equation 29: therefore: substitution of equation 20 and application of the ocp condition in equation 30 gives equation 31: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 3, r sum =3.65k , r p =11k , r ntcs = 2.61k , r ntc = 10k , dcr = 0.88m , i omax =51a and i droopmax = 40.9a, equation 31 gives r i = 606 . for resistor sensing, equation 32 gives the dc relationship of v cn (s) and i o (s). substitution of equation 32 into equation 1 gives equation 33: therefore substitution of equation 34 and application of the ocp condition in equation 30 gives equation 35: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 3, r sen =1m , i omax = 53a and i droopmax = 40.9a, equation 35 gives r i = 863 . load line slope refer to figure 9. for inductor dcr sensing, substitution of equation 29 into equation 2 gives the load line slope expression: for resistor sensing, substitution of equation 33 into equation 2 gives the load line slope expression : substitution of equation 30 and rewriting equation 36, or substitution of equation 34 and rewriting equation 37 give the same result in equation 38: one can use the full load condition to calculate r droop . for example, given i omax = 51a, i droopmax = 40.9a and ll = 1.9m , equation 38 gives r droop = 2.37k . it is recommended to start with the r droop value calculated by equation 38, and fine tune it on the actual board to get accurate load line slope. one should record the output voltage readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. compensator figure 17 shows the desired load transient response waveforms. figure 23 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e., constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the cu rrent sensing network, so the vr achieves constant output impedance as a stable system. figure 26 shows a screenshot of the spreadsheet. a vr with an active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 24 conceptually shows t1(s) measur ement set-up and figure 25 v cn r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o = (eq. 28) i droop 2 r i ---- - r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - i o = (eq. 29) r i 2r ntcnet dcr i o nr ntcnet r sum n -------------- + ?? ?? i droop ------------------------------------------------------------------------------- - = (eq. 30) r i 2 r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum n -------------- + ?? ?? ?? i droopmax ------------------------------------------------------------------------------------------------------------------------- = (eq. 31) v cn r sen n ------------ i o = (eq. 32) i droop 2 r i ---- - r sen n ------------ i o = (eq. 33) r i 2r sen i o ni droop --------------------------- = (eq. 34) r i 2r sen i omax ni droopmax -------------------------------------- = (eq. 35) ll v droop i o ----------------- - 2r droop r i ---------------------- r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - == (eq. 36) ll v droop i o ----------------- - 2r sen r droop nr i ----------------------------------------- == (eq. 37) r droop i o i droop --------------- - ll = (eq. 38) figure 23. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr
isl6363 26 fn6898.1 september 5, 2013 conceptually shows t2(s) measurem ent set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed ou tput voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measured on an isl6363 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. figure 24. loop gain t1(s) measurement set-up figure 25. loop gain t2 (s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer loop gain = channel b channel a network analyzer 20 q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer loop gain = channel b channel a network analyzer 20
isl6363 27 fn6898.1 september 5, 2013 figure 26. screenshot of the compensator design spreadsheet
isl6363 28 fn6898.1 september 5, 2013 programming resistors there are three programming resistors: r prog1 , r prog2 and r addr . table 7 shows how to select r prog1 based on v boot and imax_cr register settings. vr1 can power to 0v v boot or an internally-set v boot based on r prog1 value. when the controller works with an actual cpu, select r prog1 such that vr1 powers up to v boot = 0v as required by the svid command. in the absence of a cpu, such as testing of the only the vr, select r prog1 such that vr1 powers up to the internally-set v boot , which by default is 1.1v. determine the maximum current vr1 can support and set the imax_cr register value accordingly by selecting the appropriate r prog1 value. the cpu will read the imax_cr register and ensures that the cpu core current doesn?t exceed the value specified by imax_cr. table 8 shows how to select r prog2 based on tmax and imax_gr register setting s. there are four tmax temperatures to choose from: +120c, +110c, +105c, and +95c. there are also four imax_gr values to choose from: 35a, 30a, 25a and 20a. table 9 shows how to select r prog2 based on tmax and imax_gr register settings. there are four tmax temperatures to choose from: +120c, +110c, +105c, and +95c. there are also four imax_gr values to choose from: 35a, 30a, 25a and 20a. table 7. rprog1 programming table rprog1 (k ? ) boot (v) imax core nph = 4 (a) imax core nph = 3 (a) imax core nph = 2 (a) imax core nph = 1 (a) 7.15 1.1 100 75 50 25 13.0 1.1 108 81 54 27 20.5 1.1 116 87 58 29 27.4 1.1 124 93 62 31 38.3 1.1 132 99 66 33 52.3 1.1 140 105 70 35 66.5 1.1 148 111 74 37 80.6 0 148 111 74 37 95.3 0 140 105 70 35 1130132996633 137 0 124 93 62 31 165 0 116 87 58 29 196 0 108 81 54 27 2260100755025 open circuit 0 92694623 table 8. rprog2 programming table rprog2 (k ? ) tmax (c) imax_gr (a) 7.15 120 30 13.0 120 25 20.5 120 20 27.4 110 20 38.3 110 25 52.3 110 30 66.5 110 35 80.6 105 35 95.3 105 30 113 105 25 137 105 20 165 95 20 196 95 25 226 95 30 open circuit 95 35 table 9. raddr programming table raddr (k ? ) vr1 and vr1 svid address 00,1 7.15 0,1 13 2,3 20.5 2,3 27.4 4,5 38.3 4,5 52.3 6,7 66.5 6,7 80.6 8,9 95.3 8,9 113 a,b 137 a,b 165 c,d 196 c,d 226 0,1 open circuit 0,1
isl6363 29 fn6898.1 september 5, 2013 ntc network on the ntc and the ntcg pins the controller drives 60a curren t source out of the ntc pin and the ntcg pin alternatively at 1khz frequency with 50% duty cycle. the current source flows through the respective ntc resistor networks on the pins and creates voltages that are monitored by the controller throug h an a/d converter to generate the tzone value. table 10 shows the programming table for tzone. the user needs to scale the ntc (and ntcg) network resistance such that it generate s the ntc (and ntcg) pin voltage that corresponds to the left-most column. do not use any capacitor to filter the voltage. on adc output = 7, the controller issues thermal alert to the cpu, on adc output <7, the controller asserts the vr_hot# signal. current monitor refer to equation 18 for the imon pin current expression. referencing the ?simplified applic ation circuit? on page 6, the imon pin current flows through r imon . the voltage across r imon is expressed in equation 39: rewriting equation 38 gives equation 40: substitution of equation 40 into equation 39 gives equation 41: rewriting equation 41 and applicat ion of full load condition gives equation 42: for example, given ll = 1.9m , r droop = 2.825k , v rimon = 2.7v at i omax = 53a, equation 42 gives r imon = 25.2k . a capacitor c imon can be paralleled with r imon to filter the imon pin voltage. the r imon c imon time constant is the user?s choice. it is recommended to have a time co nstant long enough such that switching frequency ripples are removed. current balancing the isl6363 achieves current ba lancing through matching the isen pin voltages. r isen and c isen form filters to remove the switching ripple of the phase node voltages. it is recommended to use a rather long r isen c isen time constant such that the isen voltages have minimal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k and c s =0.22f. optional slew rate co mpensation circuit for 1-tick vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate. for example, the dac may change a tick (5mv) per 0.5s, controlling output voltage v core slew rate at 10mv/s. table 10. tzone programming table vntc (v) adc output %tmax tzone 0.64 0 >100% ffh 0.68 1 >100% ffh 0.72 2 >100% ffh 0.76 3 >100% ffh 0.80 4 >100% ffh 0.84 5 >100% ffh 0.88 6 100% ffh 0.92 7 97% 7fh 0.96 8 94% 3fh 1.00 9 91% 1fh 1.04 a 88% 0fh 1.08 b 85% 07h 1.12 c 82% 03h 1.16 d 79% 01h 1.2 e 76% 01h >1.2 f <76% 00h v rimon 3i droop r imon = (eq. 39) i droop i o r droop ------------------ ll = (eq. 40) v rimon 3i o ll r droop -------------------- - r imon = (eq. 41) r imon v rimon r droop 3i o ll -------------------------------------------- = (eq. 42) figure 27. optional slew rate compensation circuit for 1-tick vid transition x 1 e/a dac vid<0:6> rdroop idroop_vid vdac fb comp vcore vsssense vids rtn vss internal to ic rvid cvid vid<0:6> vfb vcore ivid idroop_vid ivid optional
isl6363 30 fn6898.1 september 5, 2013 figure 27 shows the waveforms of 1-tick vid transition. during 1-tick vid transition, the dac ou tput changes at approximately 15mv/s slew rate, but the dac cannot step through multiple vids to control the slew rate. instead, the control loop response speed determines v core slew rate. ideally, v core will follow the fb pin voltage slew rate. however, the controller senses the inductor current increase duri ng the up transition, as the i droop_vid waveform shows, and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to control v core slew rate during 1-tick vid transition, one can add the r vid -c vid branch, whose current i vid cancels i droop_vid . when v core increases, the time do main expression of the induced i droop change is: where c out is the total output capacitance. in the mean time, the r vid -c vid branch current i vid time domain expression is: it is desired to let i vid (t) cancel i droop_vid (t). so there are: and: the result is expressed in equation 47: and: for example: given ll = 1.9m , r droop = 2.37k , c out = 1320f, dv core /dt = 10mv/s and dv fb /dt = 15mv/s, equation 47 gives r vid = 2.37k and equation 48 gives c vid = 700pf. it is recommended to select the calculated r vid value and start with the calculated c vid value and tweak it on the actual board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual grou nd in small signal sense. the r vid - c vid network is between the virtual ground and the real ground, and hence has no effect on transient response. i droop t () c out ll r droop ------------------------ dv core dt ----------------- - 1e t ? c out ll ------------------------- ? ?? ?? ?? ?? = (eq. 43) i vid t () c vid dv fb dt ----------- - 1e t ? r vid c vid ------------------------------ ? ?? ?? ?? ?? = (eq. 44) c vid dv fb dt ----------- - c out ll r droop ------------------------ dv core dt ----------------- - = (eq. 45) r vid c vid c out ll = (eq. 46) r vid r droop = (eq. 47) c vid c out ll r droop ------------------------ dv core dt ----------------- - dv fb dt ----------- - ----------------- - = (eq. 48)
isl6363 31 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6898.1 september 5, 2013 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not guaranteed. please go to web to make sure you have the latest rev. date revision change september 5, 2013 fn6898.1 stamped not recommend for new designs no recommended replacement. changed products information verbiage to about intersil verbiage. updated copyright on page 1 from americas inc to americas llc september 29, 2011 fn6898.0 initial release.
isl6363 32 fn6898.1 september 5, 2013 package outline drawing l48.6x6 48 lead thin quad flat no-lead plastic package rev 1, 4/07 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 a b pin 1 index area (4x) 0.15 6 6.00 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 0.80 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ ) ( 4. 40 ) ( 48x 0 . 20 ) ( 48x 0 . 65 ) ( 44 x 0 . 40 ) 0.05 m c

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